Kise K.

Kise K.

@kisek
13
Followers
0
Following
12
Public Repos
0
Private Repos

Language Breakdown

Lines of code distribution across 12 owned repositories

32.9M Total LOC
Verilog
32,539,005 lines
98.8%
N/A
Tcl
308,901 lines
0.9%
N/A
Makefile
36,104 lines
0.1%
N/A
C
26,936 lines
0.1%
N/A
C++
9,453 lines
0.0%
N/A
I

I-Shaped Developer

I-shaped

Specialist — deep expertise in Verilog

Verilog
Tcl
Makefile
C
C++

Collaboration Network

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Kise K.
0 active collaborators

Repos

15

PRs

0

Growth

+18%

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Coding Streak

Contribution activity over the past year

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Followers 13
SahilGupta1032

Sahil Gupta

@SahilGupta1032

 vohoangnguyennnn

Vo Hoang Nguyen

@vohoangnguyennnn

 omasanori

Masanori Ogino

@omasanori

 furkanonder

Furkan Onder

@furkanonder

 nguyentrungduong

nguyentrungduong

@nguyentrungduong
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Synced via GitHub

Top Repositories

fpga_arty_a7_st7789
3 2
C++
fpga_arty_a7_dram

This is a DDR3 SDRAM (MT41K128M16JT-125) sample project for Arty A7-35T FPGA board.

3 0
Verilog
rvcore_chip1
3 0
Verilog
riscv_single
2 0
Verilog
fpga_a7-lite_hdmi

This is an HDMI output example for MicroPhase A7-Lite FPGA board with an XC7A100T (Artix-7) FPGA.

2 2
Verilog
fpga_a7-lite_led

This is an LED blinking example for MicroPhase A7-Lite FPGA board with an XC7A100T (Artix-7) FPGA.

2 0
Tcl
rvcore_chip2

RISC-V Processor

2 0
Verilog
fpga_arty_a7_uart
1 0
Verilog
fpga_a7-lite_dram

This is a DDR3 SDRAM (MT41K256M16TW-107, 512MB) sample project for A7-LITE FPGA board.

1 0
Tcl
fpga_nexys_a7_dram

This is a DDR2 SDRAM (MT47H64M16HR-25E, 128MB) sample project for Nexys A7 FPGA board.

1 0
Verilog

Open Source Impact

Contributions to external projects

0 merged PRs

No external contributions found.